The present invention relates generally to a semiconductor memory device, and more particularly to a semiconductor memory apparatus that can decrease a leakage current during a power down mode or a self refresh mode of the semiconductor memory apparatus.
A current design trend in the semiconductor memory device field is device miniaturization and high integration of the device. As the high integration and miniaturization of semiconductor memory elements progress, gate line widths of transistors have decreased and a threshold voltages has been lowered. As a result, current consumption has increased due to an off leakage current of the transistors.
Generally, a semiconductor memory apparatus includes a core area, where memory banks are located, for storing data, and a peripheral area, where one or more circuits are located, in order to have access to the core area. A leakage current is generated in turned-off transistors (transistors in the peripheral area) during a power down mode and a self refresh mode of the semiconductor memory device, the leakage current is an important factor that must be considered in the semiconductor device design in order to decrease the overall current consumption.
Accordingly, at the present time, different voltages are selectively applied to the transistors in order to decrease current consumption. That is, in order to decrease current consumption, a power supply voltage VDD is applied to the transistors in the peripheral area during a normal mode, a peripheral area voltage VPERI is applied to the transistors during a power down mode, and a core voltage VCORE is applied to the transistors during a self refresh mode.
In this case, the power supply voltage VDD is provided externally (from the outside), and the peripheral area voltage VPERI, as a peripheral area driving voltage, is lower than the power supply voltage VDD. The core voltage VCORE is used in the core area and is lower than the peripheral area voltage VPERI.
FIGS. 1A and 1B are diagrams showing a voltage supply state per node of a MOS transistor located in a peripheral area in a general semiconductor memory apparatus.
FIG. 1A shows a PMOS transistor P11. In this case, a peripheral area voltage VPERI is applied to a source terminal and a bulk terminal. FIG. 1B shows an NMOS transistor N11 that is connected to a specific node B. In this case, a ground voltage VSS is applied to a source terminal and a bulk terminal.
As such, at the present time, the same voltage is applied to the source terminal and the bulk terminal of the MOS transistor P11, N11. However, as an operation voltage of the semiconductor memory apparatus decreases and operation speed thereof improves, a margin of the threshold voltage of a transistor decreases.
Accordingly, even though the peripheral area voltage VPERI, or the core voltage VCORE that is lower than the power supply voltage VDD, is used during the power down mode or the self refresh mode of the semiconductor memory apparatus, the leakage current is still generated in the transistor while in an off state. As a result, it is difficult to decrease the current consumption of the semiconductor memory apparatus.